Job Description
RESPONSIBILITIES:
- Develop and maintain verification environment at both full chip & unit level
- Code/functional coverage analysis
- Responsible for running both RTL & gate level simulation
- Develop testing and regression methodologies
- Develop/maintain/enhance environment tools/scripts/makefiles
Desired Skills & Experience
MINIMUM REQUIREMENTS:
- BSEE/MSEE/BSCS/MSCS with 3+/5+ years of experience in ASIC design or verification
- Proficient in Verilog HDL
- Familiar with logic simulators and debug tools (VCS, NCSIM, Verdi and etc.)
- Working knowledge in C/C++, Makefile
- Must have strong programming skills in one or more scripting languages: TCL, Perl, Python
- Knowledge in one of the below areas is a big plus
+ UVM/VMM experience
+ Low power design/verification experience (Multi-Voltage, power gating,
+ UPF/APF and etc.) ARM based SoC verification experience AHB/AXI
+ architecture Embedded OS
Apply Now - Resume or CV with Job Post Title
Email: jobs@aarenconsultants.in
